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ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 1 description the ace 24c02 / 04/08/ 16b provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read - only memory (eeprom) organized as 256/512/1024/2048 words of 8 bits each. the device is optimized for use in many industrial and co mmercial applications where low - power and low - voltage operation are essential. the ace 24c02 / 04/08/ 16b is available in space - saving 8 - lead pdip, 8 - lead sop, 8 lead msop, 8 - lead tssop, 8 - pad dfn, and sot23 - 5 packages and is accessed via a two - wire serial int erface. features ? wide voltage opera tion vcc = 1.8 v to 5.5v ? operating ambient temperature - 40 ~85 ? internally organized: ACE24C02B 256*8 (2k bits) / ace24c04b 512*8 (4k bits) / ace24c08b 1024*8 (8k bits) / ace24c16b 2048*8 (16k bits) ? two - wire serial i nterface ? schmitt trigger, filtered inputs for noise suppression ? bidirectional data transfer protocol ? 1mhz(5v), 400khz(1.8v,2.5v,2.7v)compatibility ? write protect pin for hardware data protection ? 8 - byte page (2k),16 - byte page (4k,8k,16k) write modes ? partial page writes allowed ? self - timed write cycle (5ms max) ? high - reliability - endurance: 1,000,000 write cycles - data retention: 100 years absolute maximum ratings dc supply voltage - 0.3 to 6.5v input / output voltage gnd - 0.3v to v cc +0.3v operating ambient temperature - 40 to 85 storage temperature - 65 to 150 *n otice : stresses beyond those listed under absolute maximum ratings may cause permanent dam age to the device. this is a s tress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affe ct device reliability .
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 2 packaging type dip - 8 sop - 8 tssop - 8 msop - 8 tdfn sot - 23 - 5 pin configurations pin name functions a0 - a2 address inputs sda serial data scl serial clock input wp write protect gnd ground v cc power supply
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 3 block diagram
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 4 ordering information ace24c 02/04/08/16 b xx + x h d evice /p age a ddresse s (a2, a1 and a0): the a2, a1 and a0 pins are device address inputs that are hard wired for the ace 24c02 b . eight 2k devices may be addressed on a single bus system (device addressing is discussed in detail under the device addressing section). the ace 24c0 4 b uses the a2 and a1 inputs for hard wire addressing and a total of four 4k devices may be addressed on a single bus system. the a0 pin is a no connect and can be connected to ground. the ace 24c08 b only uses the a2 input for hardwire addressing and a tota l of two 8k devices may be addressed on a single bus system. the a0 and a1 pins are no connects and can be connected to ground. t he ace2 4c16b does not use the device address pins, which limits the number of devices on a single bus to one. the a0, a1, and a2 pins are no connects and can be connected to ground. s erial d ata (sda): the sda pin is bi - directional for serial data transfer. this pin is open - drain driven and may be wire - ored with any number of other open - drain or open - collector devices. s erial c lock (scl): the scl input is used to positive edge clock data into each eeprom device and negative edge clock data out of each device. w rite p rotect (wp): the ace 24c02 b / ace 24c04 b / ace 24c08 b / ace 24c16b has a write protect pin that provides hardware data p rotection. the write protect pin allows normal read/write operations when connected to ground (gnd). when the write protect pin is connected to vcc, the write protection feature is enabled and operates as shown in the following . pb - free u : tube t : tape and reel dp : dip - 8 fm : sop - 8 tm : tssop - 8 om : msop - 8 dm : tdfn bm : sot - 23 - 5 halogen - free
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 5 write protect description wp pin status part of the array protected ace24c02 b ace24c04 b ace24c08 b ace24c16 b at v cc full (2k) array full (4k) array full (8k) array upper half ( 16 k) array at gnd normal read / write operations memory organization ace 24c02 b , 2k serial eeprom: in ternally organized with 32 pages of 8 bytes each, the 2k requires an 8 - bit data word address for random word addressing. ace 24c04 b , 4k serial eeprom: internally organized with 32 pages of 16 bytes each, the 4k requires a 9 - bit data word address for random word addressing. ace24c08 b , 8k serial eeprom: internally organized with 64 pages of 16 bytes each, the 8k requires a 10 - bit data word address for random word addressing. ace 24c16 b , 16k serial eeprom: internally organized with 128 pages of 16 bytes each, the 16k requires an 11 - bit data word address for random word addressing. pin capacitance applicable over recommended operating range fro m: t a = 25 , f = 1.0 mhz, v cc = + 1.8 v. symbol test condition max units conditions c i/o input / output capacitance (sda ) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v dc characteristics applicab le over recommended operating range from : t a = - 40 to +85 , v cc = + 1.8 v to +5.5v, (unless otherwise noted). symbol parameter test condition min typ max units v cc supply voltage 1.8 5.5 v i cc1 supply current v cc = 5 .0 v, read at 100 khz 0.4 1.0 ma i cc2 supply current v cc = 5 .0 v, write at 1 00 khz 2.0 3.0 ma i sb standby current v in = v cc / gnd 1.0 a i li input leakage current v in = v cc / gnd 3.0 a i lo output leakage current v out = v cc / gnd 0.05 3.0 a v il input low level - 0. 3 v cc x0.3 v v ih input high level v cc x0.7 v cc +0. 3 v v ol 3 output low level v cc = 5.0 v, i ol = 3.0 ma 0.4 v
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 6 symbol parameter test condition min typ max units v ol 2 output low level v cc = 3.0 v, i ol = 2.1 ma 0.4 v v ol 1 output low level v cc = 1.8 v, i ol = 0.15 ma 0. 2 v ac characteristics applicable over recommended operating range from : t a = - 40 to +85 , v cc = +1. 8 v to + 5.5 v, cl = 1 ttl gate and 100 pf (unless otherwise noted). symbol parameter 1.8 - volt 3.6 - vol t units min typ max min typ max f scl clock frequency, scl 400 1000 khz t low clock pulse width low 1.2 0.6 s t high clock pulse width high 0.6 0.4 s t aa clock low to data out valid 0.05 0.9 0.05 0.55 s t buf 1 time the bus m ust be free before a new transmission can start 1.2 0.5 s t hd.sta start hold time 0.6 0.25 s t su.sta start setup time 0.6 0.25 s t hd.dat data in hold time 0 0 s t su.dat data in setup time 100 100 ns t r inputs rise time 0.3 0.3 s t f inputs fall time 300 100 ns t su.sto stop setup time 0.6 0.25 s t dh data out hold time 50 50 ns t wr 1 write cycle time (for 04b/16b) 3.3 5 3.3 5 ms t wr 1 write cycle time (for 02b/08b) 1.5 5 1.5 5 ms endurance 5.0 v, 25 , page mode 1,000,000 write cycles notes:1. this parameter is characterized and not 100% tested. 2.ac measurement conditions: rl (connects to vcc): 1.3k (2.5v,5v),10k(1.8v) input pulse voltages: 0.3 vcc to 0.7 vcc input rise and fa ll times: Q 50 ns input and output timing reference voltages: 0.5vcc the value of rl should be concerned according to the actual loading on the users system.
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 7 device operation c lock and d ata t ransitions : the sda pin is nor mally pulled hi gh with an external device. data on the sda pin may change only during scl low time periods ( see to figure 1 ). data changes during scl high periods will indicate a start or stop condition as defined below. s tart c ondition : a high - to - low transition of sda with scl high is a start condition which must precede any other command ( see to figure 2 ). s top c ondition : a low - to - high transition of sda with scl high is a stop condition. after a read sequence, the stop command will place the eeprom in a standby power mode ( see to figure 2 ). acknowledge : all addresses and data words are serially transmitted to and from the eeprom in 8 - bit words. the eeprom sends a zero to acknowledge that it has received each word. the happens during the ninth clock cycle. s tandby m ode : the ace 24c 02/04/08/16 b features a low - power standby mode which is enabled: (a) upon power - up and (b) after the receipt of the stop bit and the completion of any internal operations. memory reset : after an interruption in protocol power loss or system reset, any two - wire part can be protocol reset by following these steps: 1. clock up to 9 cycles. 2. look for sda high in each cycle while scl is high and then. 3. create a start condition. bus timing figure 1 data validity
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 8 figure 2 s tart and stop definition figure 3 output acknowledge device addressing the 2k, 4k, 8k and 16k eeprom devices all require an 8 - bit device address word following a start con dition to enable the chip for a read or write operation ( see to figure 4 ) . the device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. this is common to all the eeprom devices. the next 3 bits are the a2, a1 and a0 device address bits for the 2k eeprom. these 3 bits must compare to their corresponding hard - wired input pins. the 4k eeprom only uses the a2 and a1 device address bits with the third bit being a memory page address bit. the two device address bits must compare to their correspond ing hard - wired input pins. the a0 pin is no connect. the 8k eeprom only uses the a2 device address bit with the next 2 bits being for memory page addressing. the a2 bit must compare to its corresponding hard - wired input pin. the a1 and a0 pins are no connect.
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 9 the 16k does not use any d evice address bits but instead the 3 bits are used for memory page addressing. these page addressing bits on the 4k, 8k and 16k devices should be considered the most significant bits of the data word address which follows. the a0, a1 and a2 pins are no con nect. the eighth bit of the device address is the read/write operation select bit. a read operation is initiated if this bit is high and a write operation is initiated if this bit is low. upon a compare of the device address, the eeprom will output a z ero. if a compare is not made, the chip will return to a standby state. write operations b yte w rite : a write operation requires an 8 - bit data word address following the device address word and acknowledgment. upon receipt of this address, the eeprom will again respond with a zero and then clock in the first 8 - bit data word. following receipt of the 8 - bit data word, the eeprom will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. a t this time the eeprom enters an internally timed write cycle, t wr, to the nonvolatile memory. all inputs are disabled during this write cycle and the eeprom will not respond until the write is complete ( see to figure 5 ). p age w rite : the 2k eeprom is capa ble of an 8 - byte page write, and the 4k, 8k and 16k devices are capable of 16 - byte page writes. a page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. instead, aft er the eeprom acknowledges receipt of the first data word, the microcon troller can transmit up to seven (2k) or fifteen (4k, 8k, 16k) more data words. the eeprom will respond with a zero after each data word received. the microcontroller must terminate the page write sequence with a stop condi tion ( see to figure 6 ). the data word address lower three (2k) or four (4k, 8k, 16k) bits are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retai ning the memory page row location. when the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. if more than eight (2k) or sixteen (4k, 8k, 16k) data words are transmitted to the ee prom, the data word address will roll over and previ ous data will be overwritten. a cknowledge p olling : once the internally timed write cycle has start ed and the eeprom inputs are dis abled, acknowledge polling can be initiated. this involves sending a start condition followed by the device address word. the read/write bit is representative of the operation desired. only if the internal write cycle has completed will the eeprom respond with a zero allowing the read or write sequence to continue. read op erations read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. there are three read operations: current address read, random address read and sequential re ad.
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 10 c urrent a ddress r ead : the internal data word address counter maintains accessed address, the last and incremented by one. but for ace24c16b, only lower 8 bits of the internal data word address counter maintains the last accessed address, the high er 3 bits (p2, p1, p0) will follow the device address input at each current address read. this address stays valid between operations as long as the chip power is maintained. the address "roll over" during write is from the last byte of the current page to the first byte of the same page. once the device address with the read/write select bit set to " one " is clocked in and acknowledged by the eeprom, the current address data word is serially clocked out. the microcontroller does not respond with an input "0 " but does generate a follow ing stop condition (see figure 7 ). r andom r ead : a random read requires a dummy byte write sequence to load in the data word address. once the device address word and data word address are clocked in and acknowledged by the ee prom, the microcontroller must generate another start condition. the microcontroller now initiates a current address read by sending a device address with the read/write select bit high. the eeprom acknowledges the device address and serially clocks out th e data word. the microcontroller does not respond with a zero but does generate a following stop condition ( see figure 8 ). s equential r ead : sequential reads are initiated by either a current address read or a random address read. after the microcontroller receives a data word, it responds with an acknowledge. as long as the eeprom receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. when the memory address limit is reached, the data word address will roll over and the sequential read will continue. the sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition ( see figure 9 ). figure 4 device addre ss
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 11 figure 5 byte write figure 6 page write figure 7 current address read
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 12 figure 8 random read figure 9 sequential read figure 10 scl: serial clock, sda: serial da ta i/o
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 13 figure 11 scl: serial clock, sda: serial data i/o note: the write cycle time t wr is the time from a valid stop conition of a write sequence to the end of the internal clear/write cycle.
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 14 packaging info rmation dip - 8
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 15 packaging info rmation sop - 8
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 16 packaging info rmation tssop - 8
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 17 packaging info rmation msop - 8
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 18 packaging info rmation tdfn
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 19 packaging info rmation sot - 23 - 5
ace24 c 02 / 04/08/16b two - wire serial eeprom ver 1. 3 20 notes ace does not assume any responsibility for use as cr itical components in life support devices or systems without the express written approval of the president and general counsel of ace electronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for s urgical implant into the body, or (b) support or sustain life, and shoes failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a cri tical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. http:/ /www.ace - ele.com/

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